1. Field of the Invention
Generally, the present invention relates to the fabrication of integrated circuits, and, more particularly, to the formation of metal silicide regions on silicon-containing conductive circuit elements to decrease a sheet resistance thereof.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features are steadily decreasing to enhance device performance and functionality of the circuit. Shrinking the feature sizes, however, entails certain problems that may partially offset the advantages obtained by reducing the feature sizes. Generally, reducing the size of, for example, a transistor element such as a MOS transistor, may lead to superior performance characteristics due to a decreased channel length of the transistor element, resulting in a higher drive current capability and enhanced switching speed. Upon decreasing the channel length of the transistor elements, however, the electrical resistance of conductive lines and contact regions, i.e., of regions that provide electrical contact to the periphery of the transistor elements, becomes a major issue since the cross-sectional area of these lines and regions is also reduced. The cross-sectional area, however, determines, in combination with the characteristics of the material comprising the conductive lines and contact regions, the effective electrical resistance thereof.
Moreover, a higher number of circuit elements per unit area also requires an increased number of interconnections between these circuit elements, wherein, commonly, the number of required interconnects increases in a non-linear manner with the number of circuit elements so that the available real estate for interconnects becomes even more limited.
The majority of integrated circuits are based on silicon, that is, most of the circuit elements contain silicon regions, in crystalline, polycrystalline and amorphous form, doped and undoped, which act as conductive areas. An illustrative example in this context is a gate electrode of a MOS transistor element, which may be considered as a polysilicon line. Upon application of an appropriate control voltage to the gate electrode, a conductive channel is formed at the interface of a thin gate insulation layer and an active region of the semiconducting substrate. Although reducing the feature size of a transistor element improves device performance due to the reduced channel length, the shrinkage of the gate electrode (in the gate length direction), however, may result in significant delays in the signal propagation along the gate electrode, i.e., the formation of the channel along the entire extension (in the gate width direction) of the gate electrode. The issue of signal propagation delay is even exacerbated for polysilicon lines connecting individual circuit elements or different chip regions. Therefore, it is extremely important to improve the sheet resistance of polysilicon lines and other silicon-containing contact regions to allow further device scaling without compromising device performance. For this reason, it has become standard practice to reduce the sheet resistance of polysilicon lines and silicon contact regions by forming a metal silicide in and on appropriate portions of the respective silicon-containing regions.
With reference to FIGS. 1a–1d, a typical prior art process flow for forming metal silicide on a corresponding portion of a MOS transistor element will now be described as an illustrative example for demonstrating the reduction of the sheet resistance of silicon.
FIG. 1a schematically shows a cross-sectional view of a transistor element 100, such as a MOS transistor that is formed on a substrate 101 including a silicon-containing active region 102. The active region 102 is enclosed by an isolation structure 103, which in the present example is provided in the form of a shallow trench isolation usually used for sophisticated integrated circuits. Highly doped source and drain regions 104 including extension regions 105 that usually comprise a dopant concentration less than the highly doped regions 104 are formed in the active region 102. The source and drain regions 104 including the extension regions 105 are laterally separated by a channel region 106. A gate insulation layer 107 electrically and physically isolates a gate electrode 108 from the underlying channel region 106. Spacer elements 109 are formed on sidewalls of the gate electrode 108. A refractory metal layer 110 is formed over the transistor element 100 with a thickness required for further processing in forming metal silicide portions.
A typical conventional process flow for forming the transistor element 100, as shown in FIG. 1a, may include the following steps. After defining the active region 102 by forming the shallow trench isolations 103 by means of advanced photolithography and etch techniques, well-established and well-known implantation steps are carried out to create a desired dopant profile in the active region 102 and the channel region 106.
Subsequently, the gate insulation layer 107 and the gate electrode 108 are formed by sophisticated deposition, photolithography and anisotropic etch techniques to obtain a desired gate length, which is the horizontal extension of the gate electrode 108 as indicated by the double arrow 150 in FIG. 1a, i.e., in the plane of the drawing of FIG. 1a. Thereafter, a first implant sequence may be carried out to form the extension regions 105 wherein, depending on design requirements, additional so-called halo implants may be performed.
The spacer elements 109 are then formed by depositing a dielectric material, such as silicon dioxide and/or silicon nitride, and patterning the dielectric material by an anisotropic etch process. Thereafter, a further implant process may be carried out to form the heavily doped source and drain regions 104.
Subsequently, the refractory metal layer 110 is deposited on the transistor element 100 by, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). Preferably, a refractory metal such as titanium, cobalt and the like is used for the metal layer 110. It turns out, however, that the characteristics of the various refractory metals during the formation of a metal silicide and afterwards in the form of a metal silicide significantly differ from each other. Consequently, selecting an appropriate metal depends on further design parameters of the transistor element 100 as well as on process requirements in following processes. For instance, titanium is frequently used for forming a metal silicide on the respective silicon-containing portions wherein, however, the electrical properties of the resulting titanium silicide strongly depend on the dimensions of the transistor element 100. Titanium silicide tends to agglomerate at grain boundaries of polysilicon and therefore may increase the total electrical resistance, wherein this effect is pronounced with decreasing feature sizes so that the employment of titanium may not be acceptable for polysilicon lines, such as the gate electrode 108 having a lateral dimension, i.e., a gate length, of 0.2 μm and less.
For circuit elements having feature sizes of this order of magnitude, cobalt is preferably used as a refractory metal, since cobalt does not substantially exhibit a tendency for blocking grain boundaries of the polysilicon. In the further description of the conventional process flow, it is therefore assumed that the metal layer 110 is comprised of cobalt so as to allow the formation of the transistor element 100 as a sophisticated device having a gate length much less than 0.2 μm.
A first anneal cycle is performed to initiate a reaction between the cobalt in the layer 110 and the silicon in the drain and source regions 104 and the polysilicon in the gate electrode 108. Optionally, a titanium nitride layer having a thickness in the range of approximately 10–20 nm may be deposited above the refractory metal layer 110 prior to annealing the substrate 101 to decrease the finally obtained sheet resistance of the cobalt disilicide by reducing an oxidation of cobalt in the subsequent anneal cycles. Typically, the anneal temperature may range from approximately 450–550° C. to produce cobalt mono-silicide. Thereafter, non-reacted cobalt is selectively etched away and then a second anneal cycle is performed with a higher temperature of approximately 700° C. to convert cobalt monosilicide into cobalt disilicide.
FIG. 1b schematically shows the transistor element 100 with cobalt disilicide regions 111 formed on the drain and source region 104 and a cobalt disilicide region 112 on the gate electrode 108. Although cobalt may successfully be used for feature sizes of approximately 0.2 μm and even less, it turns out that, for further device scaling, requiring a gate length well beyond 100 nm, the sheet resistance of the cobalt disilicide enhanced gate electrode 108 increases more rapidly than expected by merely taking into account the reduced feature size of the gate electrode 108. It is believed that the drastic increase of the resistivity of the region 112 is caused by tensile stress between individual cobalt disilicide grains, thereby significantly affecting the film integrity of the cobalt disilicide when the gate length is of the order of magnitude of a single grain.
FIGS. 1c and 1d schematically represent the situation for the gate electrode 108 having a gate length L1 of approximately 200 nm compared to a gate length L2 of approximately 50 nm. FIG. 1c depicts the gate electrode 108 with the gate length L1, containing a plurality of single grains 113 arranged along the length L1, whereas, as is shown in FIG. 1d, only one single grain 113 is formed across the length L2. While the thermal stress induced during the second anneal cycle in converting cobalt monosilicide into cobalt disilicide may be compensated for by the plurality of grains across the length L1, the single grain formed across the length L2 may not allow efficient absorption of the stress and may cause an interruption of the cobalt disilicide film, as indicated by 114. As a consequence, the sheet resistance of the polysilicon gate electrode is drastically increased, thereby preventing aggressive device scaling without unduly degrading the transistor performance.
In view of the above-explained problems, there exists a need for an improved silicide formation technique, enabling further device scaling.